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general description the max11644/max11645 low-power, 12-bit, 1-/2-channel analog-to-digital converters (adcs) feature internal track/hold (t/h), voltage reference, clock, and an i 2 c-compatible 2-wire serial interface. these devices operate from a single supply of 2.7v to 3.6v(max11645) or 4.5v to 5.5v (max11644) and require only 6a at a 1ksps sample rate. autoshutdown? pow- ers down the devices between conversions, reducing supply current to less than 1a at low throughput rates. the max11644/max11645 each measure two single- ended or one differential input. the fully differential ana- log inputs are software configurable for unipolar or bipolar, and single-ended or differential operation. the full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1v to v dd . the max11645 fea- tures a 2.048v internal reference and the max11644features a 4.096v internal reference. the max11644/max11645 are available in an ultra-tiny 1.9mm x 2.2mm wlp package and an 8-pin max ? package. the max11644/max11645 are guaranteedover the extended temperature range (-40c to +85c). for pin-compatible 10-bit parts, refer to the max11646/ max11647 data sheet. applications features ? ultra-tiny 1.9mm x 2.2mm wafer level package ? high-speed i 2 c-compatible serial interface 400khz fast mode 1.7mhz high-speed mode ? single-supply 2.7v to 3.6v (max11645) 4.5v to 5.5v (max11644) ? internal reference 2.048v (max11645) 4.096v (max11644) ? external reference: 1v to v dd ? internal clock 2-channel single-ended or 1-channel fully differential ? internal fifo with channel-scan mode ? low power 670 a at 94.4ksps 230 a at 40ksps 60 a at 10ksps 6 a at 1ksps 0.5 a in power-down mode ? software-configurable unipolar/bipolar max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ _____________ maxim integrated products 1 ordering information 19-5225; rev 1; 9/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package i 2 c slave address max11644 eua+ -40c to +85c 8 max 0110110 max11645 eua+ -40c to +85c 8 max 0110110 MAX11645EWC+ -40c to +85c 12 wlp 0110110 typical operating circuit and selector guide appear at end of data sheet. autoshutdown is a trademark and max is a registered trademark of maxim integrated products, inc. + denotes a lead(pb)-free/rohs-compliant package. handheld portableapplications medical instruments battery-powered test equipment solar-powered remote systems received-signal-strengthindicators system supervision power-supply monitoring downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max11645), v dd = 4.5v to 5.5v (max11644), v ref = 2.048v (max11645), v ref = 4.096v (max11644), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c, see tables 1C5 for programming notation.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ain0, ain1, ref to gnd ..............................-0.3v to the lower of (v dd + 0.3v) and 6v sda, scl to gnd.....................................................-0.3v to +6v maximum current into any pin .........................................50ma continuous power dissipation (t a = +70c) 8-pin max (derate 4.5mw/c above +70c) ..............362mw 12-pin wlp (derate 16.1mw/c above +70c) ..........1288mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-60c to +150c lead temperature (soldering, 10s) max only .....................................................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units dc accuracy (note 2) resolution 12 bits relative accuracy inl (note 3) 1 lsb differential nonlinearity dnl no missing codes over temperatur e 1 lsb offset error 4 lsb offset-error temperature coefficient relative to fsr 0.3 ppm/c gain error (note 4) 4 lsb gain-temperature coefficient relative to fsr 0.3 ppm/c channel-to-channel offset matching 0.1 lsb channel-to-channel gain matching 0.1 lsb dynamic performance (f in(sine-wave) = 10khz, v in(p-p) = v ref , f sample = 94.4ksps) signal-to-noise plus distortion sinad 70 db total harmonic distortion thd up to the 5th harmonic -78 db spurious-free dynamic range sfdr 78 db full-power bandwidth sinad > 68db 3 mhz full-linear bandwidth -3db point 5 mhz conversion rate internal clock 7.5 conversion time (note 5) t conv external clock 10.6 s internal clock, scan[1:0] = 01 51 throughput rate f sample external clock 94.4 ksps track/hold acquisition time 800 ns internal clock frequency 2.8 mhz external clock, fast mode 60 aperture delay (note 6) t ad external clock, high-speed mode 30 ns downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ____________________________________ 3 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max11645), v dd = 4.5v to 5.5v (max11644), v ref = 2.048v (max11645), v ref = 4.096v (max11644), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c, see tables 1C5 for programming notation.) (note 1) parameter symbol conditions min typ max units analog input (ain0/ain1) unipolar 0 v ref input voltage range, single- ended and differential (note 7) bipolar 0 v ref /2 v input multiplexer leakage on/off leakage current, v ain _ = 0 or v dd 0.01 1 a input capacitance c in 22 pf internal reference (note 8) max11645 1.968 2.048 2.128 reference voltage v ref t a = +25c max11644 3.936 4.096 4.256 v reference-voltage temperature coefficient tcv ref 25 ppm/ c ref short-circuit current 2 ma ref source impedance 1.5 k external reference ref input voltage range v ref (note 9) 1 v dd v ref input current i ref f sample = 94.4ksps 40 a digital inputs/outputs (scl, sda) input-high voltage v ih 0.7 x v dd v input-low voltage v il 0.3 x v dd v input hysteresis v hyst 0.1 x v dd v input current i in v in = 0 to v dd 10 a input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v power requirements max11645 2.7 3.6 supply voltage v dd max11644 4.5 5.5 v internal reference 900 1150 f sample = 94.4ksps external clock external reference 670 900 internal reference 530 f sample = 40ksps internal clock external reference 230 internal reference 380 f sample = 10ksps internal clock external reference 60 internal reference 330 f sample =1ksps internal clock external reference 6 supply current i dd shutdown (internal ref off) 0.5 10 a power-supply rejection ratio psrr full-scale input (note 10) 0.5 2.0 lsb/v downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 4 __________________________________________________ _____________________________________ timing characteristics (figure 1) (v dd = 2.7v to 3.6v (max11645), v dd = 4.5v to 5.5v (max11644), v ref = 2.048v (max11645), v ref = 4.096v (max11644), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c, see tables 1C5 for programming notation.) (note 1) parameter symbol conditions min typ max units timing characteristics for fast mode serial-clock frequency f scl 400 khz bus free time between a stop (p) and a start (s) condition t buf 1.3 s hold time for start condition t hd,sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeated start (sr) condition t su,sta 0.6 s data hold time t hd,dat (note 11) 0 900 ns data setup time t su,dat 100 ns rise time of both sda and scl signals, receiving t r measured from 0.3v dd - 0.7v dd 20 + 0.1c b 300 ns fall time of sda transmitting t f measured from 0.3v dd - 0.7v dd (note 12) 20 + 0.1c b 300 ns setup time for stop condition t su,sto 0.6 s capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 50 ns timing characteristics for high-speed mode (c b = 400pf, note 13) serial-clock frequency f sclh (note 14) 1.7 mhz hold time, repeated start condition t hd,sta 160 ns low period of the scl clock t low 320 ns high period of the scl clock t high 120 ns setup time for a repeated start condition t su , sta 160 ns data hold time t hd , dat (note 11) 0 150 ns data setup time t su , dat 10 ns rise time of scl signal (current source enabled) t rcl 20 80 ns downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ____________________________________ 5 parameter symbol conditions min typ max units rise time of scl signal after acknowledge bit t rcl1 measured from 0.3v dd - 0.7v dd 20 160 ns fall time of scl signal t fcl measured from 0.3v dd - 0.7v dd 20 80 ns rise time of sda signal t rda measured from 0.3v dd - 0.7v dd 20 160 ns fall time of sda signal t fda measured from 0.3v dd - 0.7v dd (note 12) 20 160 ns setup time for stop condition t su , sto 160 ns capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp (notes 11 and 14) 0 10 ns timing characteristics (figure 1) (continued) (v dd = 2.7v to 3.6v (max11645), v dd = 4.5v to 5.5v (max11644), v ref = 2.048v (max11645), v ref = 4.096v (max11644), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c, see tables 1C5 for programming notation.) (note 1) note 1: all wlp devices are 100% production tested at t a = +25c. specifications over temperature limits are guaranteed by design and characterization. note 2: for dc accuracy, the max11644 is tested at v dd = 5v and the max11645 is tested at v dd = 3v with an external reference for both adcs. all devices are configured for unipolar, single-ended inputs. note 3: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range andoffsets have been calibrated. note 4: offset nulled. note 5: conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. conversion time does not include acquisition time. scl is the conversion clock in the external clock mode. note 6: a filter on the sda and scl inputs suppresses noise spikes and delays the sampling instant. note 7: the absolute input voltage range for the analog inputs (ain0/ain1) is from gnd to v dd . note 8: when the internal reference is configured to be available at ref (sel[2:1] = 11), decouple ref to gnd with a 0.1f capacitor and a 2k series resistor (see the typical operating circuit ). note 9: adc performance is limited by the converters noise floor, typically 300v p-p . note 10: measured for the max11645 as:and for the max11644, where n is the number of bits: note 11: a master device must provide a data hold time for sda (referred to v il of scl) to bridge the undefined region of scls falling edge (see figure 1). note 12: the minimum value is specified at t a = +25c. note 13: c b = total capacitance of one bus line in pf. note 14: f scl must meet the minimum clock low time plus the rise/fall times. vvvv v v fs fs n ref (. ) (. ) (. 55 45 2 55 ? ? ? ? ? ? ? ? ? ? ? ? 45 .) v vvvv v v fs fs n ref (. ) (. ) (. 36 27 2 36 ? ? ? ? ? ? ? ? ? ? ? ? 27 .) v downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 6 __________________________________________________ _____________________________________ typical operating characteristics (v dd = 3.3v (max11645), v dd = 5v (max11644), f scl = 1.7mhz, 50% duty cycle, f sample = 94.4ksps, single-ended, unipolar, t a = +25c, unless otherwise noted.) -0.5 -0.2 -0.4 -0.3 0.2 0.1 -0.1 0 0.3 0.5 0 4000 differential nonlinearity vs. digital code max11644 toc01 digital output code dnl (lsb) 1000 1500 500 2000 2500 3000 3500 0.4 -1 . 0 -0 . 4 -0 . 6 -0 . 8 -0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 integral nonlinearity vs . digital code m ax11644 toc02 digital output code inl (lsb) 0 4000 1000 1500 500 2000 2500 3000 3500 -140 -120 -100 -80 -60 -40 -20 0 10k 20k 30k 40k 50k fft plot max11644 toc03 frequency (hz) amplitude (dbc) f sample = 94.4ksps f in = 10khz 300 400350 500450 600550 650 750700 800 -40 -10 5 -25 20 35 50 65 80 supply current vs . temperature m ax11644 toc04 te m perature ( c) supply current ( a) setup byteext ref: 10111011 int ref: 11011011 internal reference m ax11644 internal reference m ax11645 external reference m ax11644 external reference m ax11645 0 0 . 2 0 . 1 0 . 4 0 . 3 0 . 5 0 . 6 2 . 75 . 2 shutdown supply current vs . supply voltage m ax11644 toc05 supply voltage (v) i dd ( a) 3 . 7 3 . 24 . 24 . 7 sda = scl = v dd 0 0 . 10 0 . 05 0 . 20 0 . 15 0 . 30 0 . 25 0 . 35 0 . 45 0 . 40 0 . 50 -40 -10 5 -25 20 35 50 65 80 shutdown supply current vs . temperature m ax11644 toc06 te m perature ( c) supply current ( a) m ax11644 m ax11645 0 200100 300 400 500 600 700 800 900 1000 0 2 04 06 08 01 0 0 analog supply current vs . conversion rate (external clock) m ax11644 toc07 conversion rate (ksps) average i dd ( a) 0 external reference internal reference always on downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package _______________________________________________________________________________________ 7 offset error vs . temperature m ax11644 toc11 te m perature ( c) offset error (lsb) 80 65 35 50 -10 5 20 -25 -0 . 9 -0 . 8 -0 . 7 -0 . 6 -0 . 5 -0 . 4 -0 . 3 -0 . 2 -0 . 1 0 -1 . 0 -40 offset error vs . supply voltage m ax11644 toc12 v dd (v) offset error (lsb) 5 . 25 . 5 4 . 7 4 . 2 3 . 7 3 . 2 -1 . 6 -1 . 2 -0 . 8 -0 . 4 0 0 . 4 0 . 8 1 . 2 1 . 6 2 . 0 -2 . 0 2 . 7 gain error vs . temperature m ax11644 toc13 te m perature ( c) gain error (lsb) 80 65 35 50 -10 5 20 -25 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 00 -40 gain error vs . supply voltage m ax11644 toc14 v dd (v) gain error (lsb) 5 . 25 . 5 4 . 7 4 . 2 3 . 7 3 . 2 -1 . 6 -1 . 2 -0 . 8 -0 . 4 0 0 . 4 0 . 8 1 . 2 1 . 6 2 . 0 -2 . 0 2 . 7 0 . 9990 0 . 9994 0 . 9992 0 . 9998 0 . 9996 1 . 0002 1 . 0000 1 . 0004 1 . 0008 1 . 0006 1 . 0010 -40 -10 5 -25 20 35 50 65 80 internal reference voltage vs . temperature m ax11644 toc09 te m perature ( c) v ref nor m alized nor m alized to value at t a = +25 c m ax11644 m ax11645 0 . 99990 0 . 99994 0 . 99992 0 . 99998 0 . 99996 1 . 00002 1 . 00000 1 . 00004 1 . 00008 1 . 00006 1 . 00010 2 . 73 . 33 . 63 . 9 3 . 04 . 24 . 54 . 85 . 15 . 4 normalized reference voltage vs . supply voltage m ax11644 toc10 v dd (v) v ref (v) m ax11644 nor m alized to reference value atv dd = 5v m ax11645 nor m alized to reference value atv dd = 3 . 3v typical operating characteristics (continued) (v dd = 3.3v (max11645), v dd = 5v (max11644), f scl = 1.7mhz, 50% duty cycle, f sample = 94.4ksps, single-ended, unipolar, t a = +25c, unless otherwise noted.) downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 8 __________________________________________________ _____________________________________ pin description pin max wlp name function 1,2 a1, a2 ain0, ain1 analog inputs 3 n.c. no connection. not internally connected. 4 a4 ref reference input/output. selected in the setup register (see ta bles 1 and 6). 5 c4 scl clock input 6 c3 sda data input/output 7 a3, b1Cb4, c2 gnd ground 8 c1 v dd positive supply. bypass to gnd with a 0.1f capacitor. sda scl ref 1 + 2 8 7 v dd gnd ain1 n.c. ain0 max top view 3 4 6 5 max11644max11645 top view (bumps on bottom) max11645 gnd ain1 gnd ref gnd gnd sda gnd gnd scl 1234 a b c wlp v dd ain0 pin configuration downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ____________________________________ 9 t hd,sta t su,dat t high t r t f t hd,dat t hd,sta s sr a scl sda t su,sta t low t buf t su,sto ps t hd,sta t su,dat t high t fcl t hd,dat t hd,sta s sr a scl sda t su,sta t low t buf t su,sto s t rcl t rcl1 hs m ode f/s m ode a) f/s- m ode 2-wire serial-interface ti m ing b) hs- m ode 2-wire serial-interface ti m ing t fda t rda t t r t f p figure 1. 2-wire serial-interface timing downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 10 _________________________________________________ _____________________________________ detailed description the max11644/max11645 analog-to-digital converters(adcs) use successive-approximation conversion tech- niques and fully differential input track/hold (t/h) cir- cuitry to capture and convert an analog signal to a serial 12-bit digital output. the max11644/max11645 measure either two single-ended or one differential input(s). these devices feature a high-speed, 2-wire serial interface supporting data rates up to 1.7mhz.figure 2 shows the simplified internal structure for the max11644/max11645. power supply the max11644/max11645 operate from a single sup-ply and consume 670a (typ) at sampling rates up to 94.4ksps. the max11645 feature a 2.048v internal ref- erence and the max11644 feature a 4.096v internal ref- erence. all devices can be configured for use with an external reference from 1v to v dd . analog input and track/hold the max11644/max11645 analog-input architecturecontains an analog-input multiplexer (mux), a fully dif- ferential track-and-hold (t/h) capacitor, t/h switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (dac) (figure 4). in single-ended mode, the analog input multiplexer connects c t/h between the analog input selected by cs[0] (see the configuration/setup bytes (write cycle) section) and gnd (table 3). in differential mode, theanalog-input multiplexer connects c t/h to the + and - analog inputs selected by cs[0] (table 4). analog input m ux ain1 ref ain0 scl sda input shift register setup register configuration register control logic reference 4 . 096v ( m ax11644) 2 . 048v ( m ax11645) internal oscillator output shift register and ra m ref t/h 12-bit adc v dd gnd max11644max11645 figure 2. simplified functional diagram v dd i ol i oh v out 400pf sda figure 3. load circuit downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 11 during the acquisition interval, the t/h switches are inthe track position and c t/h charges to the analog input signal. at the end of the acquisition interval, the t/hswitches move to the hold position retaining the charge on c t/h as a stable sample of the input signal. during the conversion interval, the switched capacitivedac adjusts to restore the comparator input voltage to 0v within the limits of a 12-bit resolution. this action requires 12 conversion clock cycles and is equivalent to transferring a charge of 11pf x (v in+ - v in- ) from c t/h to the binary weighted capacitive dac, forming a digital representation of the analog input signal.sufficiently low source impedance is required to ensure an accurate sample. a source impedance of up to 1.5k does not significantly degrade sampling accuracy. tominimize sampling errors with higher source imped- ances, connect a 100pf capacitor from the analog input to gnd. this input capacitor forms an rc filter with the source impedance limiting the analog-input bandwidth. for larger source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. when operating in internal clock mode, the t/h circuitry enters its tracking mode on the eighth rising clock edge of the address byte. see the slave address section. the t/h circuitry enters hold mode on the falling clockedge of the acknowledge bit of the address byte (the ninth clock pulse). a conversion or a series of conver- sions is then internally clocked and the max11644/ max11645 hold scl low. with external clock mode, thet/h circuitry enters track mode after a valid address on the rising edge of the clock during the read (r/ w = 1) bit. hold mode is then entered on the rising edge of thesecond clock pulse during the shifting out of the first byte of the result. the conversion is performed during the next 12 clock cycles. the time required for the t/h circuitry to acquire an input signal is a function of the input sample capaci- tance. if the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the minimum time needed for the signal to be acquired. it is calculated by: t acq 95 (r source + r in ) x c in where r source is the analog-input source impedance, r in = 2.5k , and c in = 22pf. t acq is 1.5/f scl for internal clock mode and t acq = 2/f scl for external clock mode. analog input bandwidth the max11644/max11645 feature input-tracking cir-cuitry with a 5mhz small-signal bandwidth. the 5mhz input bandwidth makes it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using under sampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. track track hold c t/h c t/h track track hold ain0 ain1 gnd analog input m ux capacitive dac ref capacitive dac ref max11644max11645 hold hold track hold v dd /2 figure 4. equivalent input circuit downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 12 _________________________________________________ _____________________________________ analog input range and protection internal protection diodes clamp the analog input to v dd and gnd. these diodes allow the analog inputs to swingfrom (gnd - 0.3v) to (v dd + 0.3v) without causing dam- age to the device. for accurate conversions, the inputsmust not go more than 50mv below gnd or above v dd . single-ended/differential input the sgl/ dif of the configuration byte configures the max11644/max11645 analog-input circuitry for single-ended or differential inputs (table 2). in single-ended mode (sgl/ dif = 1), the digital conversion results are the difference between the analog input selected bycs[0] and gnd (table 3). in differential mode (sgl/ dif = 0), the digital conversion results are the differ- ence between the + and the - analog inputs selectedby cs[0] (table 4). unipolar/bipolar when operating in differential mode, the bip/ uni bit of the set-up byte (table 1) selects unipolar or bipolaroperation. unipolar mode sets the differential input range from 0 to v ref . a negative differential analog input in unipolar mode causes the digital output codeto be zero. selecting bipolar mode sets the differential input range to v ref /2. the digital output code is bina- ry in unipolar mode and twos complement in bipolarmode. see the transfer functions section. in single-ended mode, the max11644/max11645always operate in unipolar mode irrespective of bip/ uni . the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . 2-wire digital interface the max11644/max11645 feature a 2-wire interfaceconsisting of a serial-data line (sda) and serial-clock line (scl). sda and scl facilitate bidirectional commu- nication between the max11644/max11645 and the master at rates up to 1.7mhz. the max11644/ max11645 are slaves that transfer and receive data. the master (typically a microcontroller) initiates data transfer on the bus and generates the scl signal to permit that transfer. sda and scl must be pulled high. this is typically done with pullup resistors (750 or greater) (see the typical operating circuit ). series resistors (rs) are optional. they protect the input architecture of the max11644/max11645 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl clockcycle. a minimum of 18 clock cycles are required to transfer the data in or out of the max11644/max11645. the data on sda must remain stable during the highperiod of the scl clock pulse. changes in sda while scl is stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start (s)condition, a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop (p) condition, a low-to-high transition on sda while scl is high (figure 5). a repeated start (sr) condition can be used in place of a stop condition to leave the bus active and the interface mode unchanged (see the hs mode section). acknowledge bits data transfers are acknowledged with an acknowledgebit (a) or a not-acknowledge bit ( a ). both the master and the max11644/max11645 (slave) generateacknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 6). to generate a not-acknowledge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. scl sda sp sr figure 5. start and stop conditions scl sda s not-acknowledge acknowledge 12 89 figure 6. acknowledge bits downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 13 slave address a bus master initiates communication with a slavedevice by issuing a start condition followed by a slave address. when idle, the max11644/max11645 continuously wait for a start condition followed by their slave address. when the max11644/max11645 recognize their slave address, they are ready to accept or send data. the slave address is factory programmed to 0110110. the least significant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the max11644/max11645(r/ w = 0 selects a write condition, r/ w = 1 selects a read condition). after receiving the address, themax11644/max11645 (slave) issues an acknowledge by pulling sda low for one clock cycle. bus timing at power-up, the max11644/max11645 bus timing isset for fast-mode (f/s mode), which allows conversion rates up to 22.2ksps. the max11644/max11645 must operate in high-speed mode (hs mode) to achieve con-version rates up to 94.4ksps. figure 1 shows the bus timing for the max11644/max11645s 2-wire interface. hs mode at power-up, the max11644/max11645 bus timing isset for f/s mode. the bus master selects hs mode by addressing all devices on the bus with the hs-mode master code 0000 1xxx (x = dont care). after suc- cessfully receiving the hs-mode master code, the max11644/max11645 issue a not-acknowledge, allow- ing sda to be pulled high for one clock cycle (figure 8). after the not-acknowledge, the max11644/ max11645 are in hs mode. the bus master must then send a repeated start followed by a slave address to initiate hs mode communication. if the master gener- ates a stop condition, the max11644/max11645 return to f/s mode. 01 1 1 0 1 0 r/w a slave address s scl sda 123456789 m ax11644/ m ax11645 see ordering infor m ation for slave address options and details . figure 7. max11644/max11645 slave address byte 000 1 0x x x a hs- m ode m aster code scl sda s sr f/s m ode hs m ode figure 8. f/s-mode to hs-mode transfer downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 14 _________________________________________________ _____________________________________ configuration/setup bytes (write cycle) a write cycle begins with the bus master issuing astart condition followed by seven address bits (figure 7) and a write bit (r/ w = 0). if the address byte is successfully received, the max11644/max11645(slave) issues an acknowledge. the master then writes to the slave. the slave recognizes the received byte as the set-up byte (table 1) if the most significant bit (msb) is 1. if the msb is 0, the slave recognizes that byte as the configuration byte (table 2). the master can write either one or two bytes to the slave in anyorder (setup byte, then configuration byte; configura- tion byte, then setup byte; setup byte or configuration byte only; figure 9). if the slave receives a byte suc- cessfully, it issues an acknowledge. the master ends the write cycle by issuing a stop condition or a repeat- ed start condition. when operating in hs mode, a stop condition returns the bus into f/s mode (see the hs mode section). b) two-byte write cycle slave to m aster m aster to slave s 1 slave address a 71 1 w setup or configuration byte setup or configuration byte 8 p or sr 1 a 1 m sb deter m ines whether setup or configuration byte s 1 slave address a 71 1 w setup or configuration byte 8 p or sr 1 a 1 m sb deter m ines whether setup or configuration byte a 1 8 a) one-byte write cycle nu m ber of bits nu m ber of bits figure 9. write cycle bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg sel2 sel1 sel0 clk bip/ uni rst x bit name description 7 reg register bit. 1 = setup byte, 0 = configuration byte (table 2). 6 sel2 5 sel1 4 sel0 three bits select the reference voltage (table 6).default to 000 at power-up. 3 clk 1 = external clock, 0 = internal clock. defaults to 0 at power-up. 2 bip/ uni 1 = bipolar, 0 = unipolar. defaults to 0 at power-up (see the unipolar/bipolar section). 1 rst 1 = no action, 0 = resets the configuration register to default. setup register remains unchanged. 0 x dont-care bit. this bit can be set to 1 or 0. table 1. setup byte format downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 15 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg scan1 scan0 x x x cs0 sgl/ dif bit name description 7 reg register bit. 1 = setup byte (see table 1), 0 = configuration byte. 6 scan1 5 scan0 scan select bits. two bits select the scanning configuration (table 5). default to 00 at power-up. 4x 3x 2x 1 cs0 channel select bit. cs0 selects which analog input channels are to be used for conversion(tables 3 and 4). default to 0000 at power-up. 0 sgl/ dif 1 = single-ended, 0 = differential (tables 3 and 4). defaults to 1 at power-up. see the single- ended/differential input section. table 2. configuration byte format cs0 ain0 ain1 gnd 0+ - 1+ - x = dont care. table 3. channel selection in single-ended mode (sgl/ dif = 1) cs0 ain0 ain1 0+ - 1-+ table 4. channel selection in differential mode (sgl/ dif = 0) downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 16 _________________________________________________ _____________________________________ data byte (read cycle) a read cycle must be initiated to obtain conversionresults. read cycles begin with the bus master issuing a start condition followed by seven address bits and a read bit (r/ w = 1). if the address byte is successfully received, the max11644/max11645 (slave) issues anacknowledge. the master then reads from the slave. the result is transmitted in 2 bytes; first 4 bits of the first byte are high, then msb through lsb are consecutively clocked out. after the master has received the byte(s), it can issue an acknowledge if it wants to continue read- ing or a not-acknowledge if it no longer wishes to read. if the max11644/max11645 receive a not-acknowl- edge, they release sda, allowing the master to generate a stop or a repeated start condition. see the clock modes and scan mode sections for detailed information on how data is obtained and converted. clock modes the clock mode determines the conversion clock andthe data acquisition and conversion time. the clock mode also affects the scan mode. the state of the set- up bytes clk bit determines the clock mode (table 1). at power-up, the max11644/max11645 are defaulted to internal clock mode (clk = 0). internal clock when configured for internal clock mode (clk = 0), themax11644/max11645 use their internal oscillator as the conversion clock. in internal clock mode, the max11644/max11645 begin tracking the analog input after a valid address on the eighth rising edge of the clock. on the falling edge of the ninth clock, the analogsignal is acquired and the conversion begins. while converting the analog input signal, the max11644/ max11645 hold scl low (clock stretching). after the conversion completes, the results are stored in internal memory. if the scan mode is set for multiple conver- sions, they all happen in succession with each addi- tional result stored in memory. the max11644/ max11645 contain two 12-bit blocks of memory. once all conversions are complete, the max11644/ max11645 release scl, allowing it to be pulled high. the master can now clock the results out of the memo- ry in the same order the scan conversion has been done at a clock rate of up to 1.7mhz. scl is stretched for a maximum of 8.3s per channel (see figure 10). the device memory contains all of the conversion results when the max11644/max11645 release scl. the converted results are read back in a first-in-first-out (fifo) sequence. the memory contents can be read continuously. if reading continues past the result stored in memory, the pointer wraps around and points to the first result. note that only the current conversion results are read from memory. the device must be addressed with a read command to obtain new conversion results. the internal clock modes clock stretching quiets the scl bus signal, reducing the system noise during con- version. using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus. clock stretch b) scan m ode conversions with internal clock s 1 slave address a a 71 1 r clock stretch nu m ber of bits p or sr 1 8 result 8 lsbs 8 result 4 m sbs a a 1 a) single conversion with internal clock s 1 slave address 71 1 r nu m ber of bits p or sr 1 8 result 1 ( 4 m sbs) a 1 a 8 result 1 (8 lsbs) a 8 result n (8lsbs) a 1 8 result n (4 m sbs) slave to m aster m aster to slave clock stretch t acq1 t conv2 t acq2 t convn t acqn t conv t acq 1 1 t conv1 figure 10. internal clock mode read cycles downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 17 external clock when configured for external clock mode (clk = 1),the max11644/max11645 use the scl as the conver- sion clock. in external clock mode, the max11644/ max11645 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. two scl clock cycles later, the analog signal is acquired and the conversion begins. unlike the internal clock mode, converted data is available immediately after the first four empty high bits. the device continuously con- verts input channels dictated by the scan mode until given a not-acknowledge. there is no need to read- dress the device with a read command to obtain new conversion results (see figure 11). the conversion must complete in 1ms, or droop on the track-and-hold capacitor degrades conversion results. use internal clock mode if the scl clock periodexceeds 60s. the max11644/max11645 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. below 40ksps, internal clock mode is recom- mended due to much smaller power consumption. scan mode scan0 and scan1 of the configuration byte set thescan mode configuration. table 5 shows the scanning configurations. the scanned results are written to memo- ry in the same order as the conversion. read the results from memory in the order they were converted. each result needs a 2-byte transmission; the first byte begins with 4 empty bits, during which sda is left high. each byte has to be acknowledged by the master or the mem- ory transmission is terminated. it is not possible to read the memory independently of conversion. slave address t conv1 t acq1 t acq2 t convn t acqn t conv t acq nu m ber of bits nu m ber of bits 1 8 a 1 s 1 a 71 1 r s 1 71 1 r p or sr 1 8 a 1 a 8 a 8 b) scan m ode conversions with external clock 1 1 slave address p or sr result (8 lsbs) 8 a 1 result (4 m sbs) a) single conversion with external clock slave to m aster m aster to slave result 1 (4 m sbs) result 2 (8 lsbs) result n (8 lsbs) a 1 8 result n (4 m sbs) a figure 11. external clock mode read cycle scan1 scan0 scanning configuration 0 0 scans up from ain0 to the input selected by cs0. 0 1 converts the input selected by cs0 eight times (see tables 3 and 4).* 1 0 reserved. do not use. 1 1 converts the input selected by cs0.* * when operating in external clock mode, there is no difference between scan[1:0] = 01 and scan[1:0] = 11, and converting occurs perpetually until not-acknowledge occurs. table 5. scanning configuration downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package 18 _________________________________________________ _____________________________________ applications information power-on reset the configuration and setup registers (tables 1 and 2)default to a single-ended, unipolar, single-channel con- version on ain0 using the internal clock with v dd as the reference. the memory contents are unknown afterpower-up. automatic shutdown automatic shutdown occurs between conversions whenthe max11644/max11645 are idle. all analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. when operating in external clock mode, a stop, not- acknowledge, or repeated start condition must be issued to place the devices in idle mode and benefit from automatic shutdown. a stop condition is not nec- essary in internal clock mode to benefit from automatic shutdown because power-down occurs once all con- version results are written to memory (figure 10). when using an external reference or v dd as a reference, all analog circuitry is inactive in shutdown and supply cur-rent is less than 0.5a. the digital conversion results obtained in internal clock mode are maintained in mem- ory during shutdown and are available for access through the serial interface at any time prior to a stop or a repeated start condition. when idle, the max11644/max11645 continuously wait for a start condition followed by their slave address (see the slave address section). upon reading a valid address byte, the max11644/max11645 power up. theinternal reference requires 10ms to wake up, so when using the internal reference it should be powered up 10ms prior to conversion or powered continuously. wake-up is invisible when using an external reference or v dd as the reference. automatic shutdown results in dramatic power savings,particularly at slow conversion rates and with internal clock. for example, at a conversion rate of 10ksps, the average supply current for the max11645 is 60a (typ) and drops to 6a (typ) at 1ksps. at 0.1ksps the aver- age supply current is just 1a, or a minuscule 3w of power consumption. see average supply current vs. conversion rate (external clock) in the typical operating characteristics section). reference voltage sel[2:0] of the setup byte (table 1) control the refer-ence configuration (table 6). internal reference the internal reference is 4.096v for the max11644 and2.048v for the max11645. when ref is configured to be an internal reference output (sel[2:1] = 11), decou- ple ref to gnd with a 0.1f capacitor and a 2k series resistor (see the typical operating circuit ). once powered up, the reference always remains on untilreconfigured. the internal reference requires 10ms to wake up and is accessed using sel0 (table 6). when in shutdown, the internal reference output is in a high- impedance state. the reference should not be used to supply current for external circuitry. the internal refer- ence does not require an external bypass capacitor and works best when left unconnected (sel1 = 0). external reference the external reference can range from 1v to v dd . for maximum conversion accuracy, the reference must beable to deliver up to 40a and have an output imped- ance of 500k or less. if the reference has a higher output impedance or is noisy, bypass it to gnd asclose as possible to ref with a 0.1f capacitor. sel2 sel1 sel0 reference voltage ref internal reference state 00x v dd not connected always off 0 1 x external reference reference input always off 1 0 0 internal reference not connected* always off 1 0 1 internal reference not connected* always on 1 1 0 internal reference reference output always off 1 1 1 internal reference reference output always on table 6. reference voltage and ref format x = dont care. *preferred configuration for internal reference. downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 19 transfer functions output data coding for the max11644/max11645 isbinary in unipolar mode and twos complement in bipo- lar mode with 1 lsb = (v ref /2 n ) where n is the number of bits (12). code transitions occur halfway betweensuccessive-integer lsb values. figures 12 and 13 show the input/output (i/o) transfer functions for unipo- lar and bipolar operations, respectively. layout, grounding, and bypassing only use pcbs. wire-wrap configurations are not rec-ommended since the layout should ensure proper sep- aration of analog and digital traces. do not run analog and digital lines parallel to each other, and do not lay- out digital signal paths underneath the adc package. use separate analog and digital pcb ground sections with only one star point (figure 14) connecting the two ground systems (analog and digital). for lowest noise operation, ensure the ground return to the star grounds power supply is low impedance and as short as possi- ble. route digital signals far away from sensitive analog and reference inputs. high-frequency noise in the power supply (v dd ) could influence the proper operation of the adcs fast compara-tor. bypass v dd to the star ground with a network of two parallel capacitors, 0.1f and 4.7f, located as close aspossible to the max11644/max11645 power-supply pin. minimize capacitor lead length for best supply noiserejection, and add an attenuation resistor (5 ) in series with the power supply if it is extremely noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the valueson an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the max11644/max11645s inl is measured using the endpoint. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when anactual sample is taken. max11644max11645 output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2 lsb fs = v ref zs = gnd input voltage (lsb) 1 lsb = v ref 4096 figure 12. unipolar transfer function 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs 0 input voltage (lsb) output code zs = 0 +fs - 1 lsb fs = v ref 2 -fs = -v ref 2 max11644max11645 1 lsb = v ref 4096 figure 13. bipolar transfer function downloaded from: http:///
max11644/max11645 20 _________________________________________________ _____________________________________ signal-to-noise ratio for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adcs reso- lution (n bits): snr max[db] = 6.02db x n + 1.76db in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of thefundamental input frequencys rms amplitude to the rms equivalent of all other adc output signals. effective number of bits effective number of bits (enob) indicates the globalaccuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quanti- zation noise only. with an input range equal to the adcs full-scale range, calculate the enob as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rmssum of the input signals first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of therms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor- tion component. thd vvvv v log = +++ ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 ?? ? ? ? ? ? ? ? sinad db signal noise thd rms rms rms () log = + ? ? ? 20 ?? ? ? gnd v logic = 3v/5v 3v or 5v supplies dgnd 3v/5v gnd *optional 4 . 7 f r* = 5 0 . 1 f v dd digital circuitry max11644max11645 figure 14. power-supply grounding connection low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package ___________________________________________________ ___________________________________ 21 *optional r s * r s * analog inputs c sda scl gnd v dd sda scl ain0ain1 rc network* ref 3 . 3v or 5v 5v r p c ref 0 . 1 f r p 5v max11644max11645 0 . 1 f 2k typical operating circuit chip information process: bicmos part input channels internal reference (v) supply voltage (v) inl (lsb) max11644 2 single- ended/1 differential 4.096 4.5 to 5.5 1 max11645 2 single- ended/1 differential 2.048 2.7 to 3.6 1 selector guide package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 max u8cn+1 21-0036 90-0092 12 wlp w121c2+1 21-0009 refer to application note 1891 downloaded from: http:///
max11644/max11645 low-power, 1-/2-channel, i 2 c, 12-bit adcs in ultra-tiny 1.9mm x 2.2mm package maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release 1 9/10 added the wlp package to the ordering information , absolute maimum ratings , pin configuration , pin description , and package information sections 1, 2, 8, 20 downloaded from: http:///

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